The present invention relates to a pattern transfer apparatus for transferring a circuit pattern of a semiconductor apparatus onto a substrate to be processed, and a management system thereof.
In recent years, as integration of LSIs has been developed, a critical dimension (CD) of the circuit required for a semiconductor device has become smaller and smaller. The following table 1 shows a trend of semiconductor devices (DRAMs and LOGICs).
TABLE 1 ______________________________________ Trends of Semiconductor Device ______________________________________ RESOLUTION (.mu.m) 1995 1998 2001 2004 2007 0.35 0.25 0.18 0.13 0.10 DRAM (bits) 64 M 256 M 1 G 4 G 16 G Chip Size DRAM (mm .times. mm) 10 .times. 20 12 .times. 24 15 .times. 30 18 .times. 36 22 .times. 44 LOGIC (mm .times. mm) 16 .times. 16 18 .times. 18 19 .times. 19 21 .times. 21 23 .times. 23 MASK 5X 4X 4X 4X 4X MAGNIFICATION MASK PATTERN 70 44 32 26 18 POSITION PRECISION (nm) MASK PATTERN 50-35 40-25 30-18 20-13 16-10 LINE WIDTH UNIFORMITY (nm) ______________________________________
Manufacture of these semiconductor devices generally adopts the following method. Specifically, a mercury-vapor lamp and xenon-vapor lamp (g-line or I-line), or a deep ultraviolet source (KrF or ArF) having a short wavelength is used as a light source, and any of several kinds of original masks, on which a desired circuit pattern is formed, is positioned with high precision with respect to a wafer. Thereafter, the pattern is minified and transferred onto an exposure region on the wafer at a magnification of 1/5 or 1/4. Discussion has been made about a possibility that an exposing apparatus (or pattern transfer apparatus) using a soft X-ray having a wavelength of about 1 nm or an electron beam direct drawing apparatus may be substituted for optical lithography, with respect to a pattern which has a size of 1 .mu.m or less, due to resolution limits from wavelengths of light. However, there has been a prospect that optical lithography can work effectively in the generation of 1 G-bit DRAM and at the beginning of 4 G-bit DRAM, because of progress of optical lithography techniques.
As long as an exposing apparatus is concerned, such optical lithography techniques have improved the performance in precision or times to align a mask with a wafer by reconsideration of alignment methods of TTL (Through The Lens) or TTR (Through The Reticle) and alignment algorithms of EGA (Enhanced Global Alignment). Those techniques have also achieved a high throughput (i.e., the number of wafers exposed per unit time) by improvements in apparatuses, i.e., preparing wafer stages with a higher speeds and higher precision, by adopting frictionless guides for stage components and reducing weights of stages.
In addition, attempts to further improve the resolution and the depth of focus and process developments such as a surface imaging method and the like have been made, by adopting super-resolution exposure techniques represented by a phase-shift mask, an off-axis illumination method, a pupil plain filtering method, and the like.
Meanwhile, as a result to have increased a pattern area of a semiconductor device accordingly as the integration has been improved, a large aperture lens 31 for transferring a circuit pattern area 30 on a mask 34, as shown in FIG. 1A has been required. The following table 2 shows the relationship between the chip size and the lens aperture required.
TABLE 2 ______________________________________ Chip Size and Required Lens Aperture ______________________________________ Chip Size/2 Chip 20 .times. 20 24 .times. 24 30 .times. 30 36 .times. 36 44 .times. 44 DRAM (mm .times. mm) 4x Mask 113 136 170 204 249 Transfer Lens Aperture (mm) ______________________________________
The larger the chip size is, the larger the lens aperture required. Further, in accordance with improvements in resolution, demands have arisen for lenses having less distortion over the entire exposure surface. However, as indicated in "Super Precision Process Technique (First Volume), p. 106, 1993", it is very difficult to prepare a large aperture lens having less distortion over the entire exposure surface than a conventional lens.
However, by scanning an exposure surface 32 like a rectangular slit as shown in FIG. 1B in the direction indicated by an arrow 33, a scanning type exposure apparatus capable of enlarging the exposure area in a certain direction has been developed, so that semiconductor devices of the class of 256M- and 1 G-bit DRAMs can be manufactured. In this case, since the lens aperture (equal to the length of the exposure surface 32) required can be reduced and since the area in the vicinity of the center of the lens 31' is used, more advantages can be obtained for an optical system than in the case of conventional-transfer.
As for scanning methods, there are two methods one being a method of relatively scanning a mask and a wafer, with an optical system fixed and the other being a method of relatively scanning an optical system and a wafer, with a mask fixed. In any of the methods, the mask or optical system and the wafer must be driven with accurate synchronization, in comparison with a conventional exposure apparatus in which an wafer is relatively stepped and repeated. Therefore, control of mask stages and wafer stages is complicated.
However, in an exposure apparatus intended for manufacture of semiconductor devices in the class of 256M and 1 G-bit DRAMs as described above, since the illumination system, the lens system, the driving system, and the control system of the apparatus have special functions different from those of a conventional apparatus, the apparatus is very expensive. Further, since improvements in precision of patterns such as linearity and uniformity of patterns are required for a mask used for an exposure apparatus having a resolution equal to or less than the exposure wavelength, a mask itself has come to be expensive.
It has thus been recognized that increases in costs cannot be avoided for the purpose of manufacturing the newest semiconductor devices. Therefore, from the view point of COO (Cost Of Ownership), it is indispensable to introduce optimization of the entire production system for manufacturing semiconductor devices, in order to reduce costs of the entire system.
This is, for example, a way of thinking called Mix and Match of using different exposure apparatuses mixed and matched for purposes, e.g., a newest scanning type exposure apparatus is used, with respect to exposure of layers requiring a high resolution, while a conventional apparatus is applied to exposure of layers which do not much require a high resolution. However, from the view point of COO as described above, in case where consideration is additionally taken into the designed area of a clean room and throughputs of individual apparatuses, it has been taught that use of a newest apparatus having a small design area and a high throughput results in more advantages even in view of cost performance than use of a conventional apparatus having a large design area and a low throughput, in order to reduce the price of a semiconductor device.
By further developing the way of thinking of Mix and Match from the above point of view, a lower-reducing exposure apparatus has appeared which has a high throughput and which is based on a thought of performing exposure with a reduced reducing with respect to exposure of layers which do not require a high resolution. In this case, even a 1/2-reducing exposure apparatus having a reducing two times lower than the reducing of 1/4 enables transfer of information which is four times more than information that can be transferred by an apparatus of main current trend, onto a pattern 35 which is drawn on the same area on a mask 34 as in case of transfer, as shown in FIG. 1C. Therefore, the throughput can be greatly improved.
As another method of improving the throughput of the entire exposure apparatus, a method of enlarging the mask size has been discussed. As for the method of enlarging the mask size, it is considered that the enlarged size of a substrate and an increase in mask price caused by new developments in a processing apparatus, caused by the enlarged size of a substrate, will lead to an increase in price of a semiconductor device. On the other side, it is also considered that costs will be reduced down as a whole if the production ability is improved.
If the mask size is changed to a size equivalent to a 7-, 8-, or 9-inch square which is larger than a substrate of 6-inch square as a main trend in the class of 64M-bit DRAMs, the information amount which can be transferred by one time of exposure is naturally increased, so that improvements in throughputs can be expected. The following Table 3 show how many patterns can be obtained in case where an alignment mark 43 of an exposure apparatus and a margin for a pellicle protect region 41 for protecting a pattern surface 42 are obtained in an area of width 15 mm in a mask 40 and where regions required for a 1 G- or 4 G-bit DRAM are spread on each exposure region, as shown in FIG. 2.
TABLE 3 __________________________________________________________________________ Pattern Regions Obtained Per Mask of DRAMs __________________________________________________________________________ 256 M 1 G First Second Third Fourth First Second DRAM 64 M Generation Generation Generation Generation Generation Generation __________________________________________________________________________ REGION SIZE 7 .times. 13 13 .times. 25 11 .times. 22 10 .times. 19 8 .times. 17 15 .times. 31 14 .times. 25 (mm .times. mm) Exposure 25 mm .times. Scanning Length 30 mm .times. Scanning Length Region 6-inch 6 2 2 3 3 2 2 Square 7-inch 9 3 3 4 4 2 2 Square 8-inch 9 3 4 4 5 2 3 Square 9-inch 9 3 4 5 6 3 4 Square __________________________________________________________________________ 1G 4G Fourth First Second Third Fourth DRAM Third Generation Generation Generation Generation Generation Generation __________________________________________________________________________ REGION SIZE 12 .times. 23 10 .times. 20 19 .times. 38 17 .times. 33 14 .times. 29 12 .times. 25 (mm .times. mm) Exposure 30 mm .times. Scanning 35 mm .times. Scanning Length Region Length 6-inch 2 Square 7-inch 3 3 1 2 2 3 Square 8-inch 4 6 2 2 3 3 Square 9-inch 4 6 2 3 3 6 Square __________________________________________________________________________
From simple comparison between areas, by adopting a mask of 9-inch square, it is possible to prospect an exposure region which is, at highest, two times larger than that of a conventional 6-inch square mask of main trend by exposure of one time. In Table 3, a chip of the first generation is a chip under development or of prototype, chips of the second and third generations are chips manufactured on a line developed for manufacturing chips of the generations, and a chip of the fourth generation is manufactured by a lithography technique of a next generation so that chips of the fourth generation can be manufactured with the highest efficiency.
The following Table 4 shows a case of a LOGIC. Since a pattern region required is a square and since a larger region is required than a DRAM, the number of pattern regions which can be maintained is small on a mask. However, it is considered that the exposure region which can be maintained is, at most, two times larger by adopting a mask of 9-inch square like in the case of a DRAM.
TABLE 4 ______________________________________ Pattern Regions Maintained Per Mask for LOGIC ______________________________________ LOGIC 256 M 1 G 4 G Region Size 19 .times. 19 21 .times. 21 23 .times. 23 (mm .times. mm) Exposure 25 mm .times. Scanning 30 mm .times. 35 mm .times. Region Length Scanning Length Scanning Length 6-inch Square 1 1 -- 7-inch Square 1 1 1 8-inch Square 2 2 1 9-inch Square 2 2 2 ______________________________________
Meanwhile, the price of an exposure apparatus is expected to increase since a lens having less distortion and a large aperture and an illumination system with a high efficiency are required as the resolution and the region which can be exposed are increased from 256M-bit to 4 G-bit DRAMs. Further, as for the price of the mask like the price of the exposure apparatus, it is necessary to consider developments in a Cr-deposition apparatus for forming a Cr-film and a coater for uniformly applying resist, in addition to an increase in price of blanks themselves.
Supposing a scanning type exposure apparatus of a type in which a mask and a wafer are scanned simultaneously when fixing an optical system, throughputs are calculated in case where masks of 6-inch, 7-inch, 8-inch and 9-inch are used. The calculation results in case of DRAMs are shown in the following Table 5 and those in case of LOGICs are shown in the following Table 6. Here, the values are defined as follows. I.e., the wafer size supposed is 12-inch and the field size is calculated, supposing that the exposure dose is 25 mJ/cm.sup.2 and the exposure power is 360 mW/cm.sup.2 on the basis of the lens aperture supposed for each generation and that the throughput of an exposure apparatus which is capable of exposing a 6-inch square and has a resolution equivalent to a 256M-bit DRAM is the standard.
TABLE 5 __________________________________________________________________________ Throughputs of DRAMs __________________________________________________________________________ 256 M 1 G First Second Third Fourth First Second DRAM 64 M Generation Generation Generation Generation Generation Generation __________________________________________________________________________ REGION SIZE 7 .times. 13 13 .times. 25 11 .times. 22 10 .times. 19 8 .times. 17 15 .times. 31 14 .times. 25 (mm .times. mm) Exposure 25 mm .times. Scanning Length 30 mm .times. Scanning Length Region 6-inch 1 1 1 1 1 1 1 Square 7-inch 1.17 1.16 1.13 1.12 0.97 1.00 1.00 Square 8-inch 1.17 1.16 1.22 1.22 1.11 1.00 1.07 Square 9-inch 1.17 1.16 1.22 1.19 1.34 1.21 1.23 Square __________________________________________________________________________ 1 G 4 G Fourth First Second Third Fourth DRAM Third Generation Generation Generation Generation Generation Generation __________________________________________________________________________ REGION SIZE 12 .times. 23 10 .times. 20 19 .times. 38 17 .times. 33 14 .times. 29 12 .times. 25 (mm .times. mm) Exposure 30 mm .times. Scanning 35 mm .times. Scanning Length Region Length 6-inch 1 Square 7-inch 1.15 1 1 1 1 1 Square 8-inch 1.11 1.30 1.58 1.00 1.14 1.29 Square 9-inch 1.27 1.30 1.58 1.06 1.14 1.58 Square __________________________________________________________________________
TABLE 6 ______________________________________ Throughputs of LOGIC ______________________________________ LOGIC 256 M 1 G 4 G Region Size 19 .times. 19 21 .times. 21 23 .times. 23 (mm .times. mm) Exposure 25 mm .times. Scanning 30 mm .times. 35 mm .times. Region Length Scanning Length Scanning Length 6-inch Square 1 1 -- 7-inch Square 1 1 1 8-inch Square 1.33 1.27 1 9-inch Square 1.33 1.27 1.16 ______________________________________
From Tables 5 and 6, throughputs are averagely improved by 1.27 times by using 9-inch square substrates than those with 6-inch square substrates, including a peak in which the throughput obtained by using a substrate of 9-inch square for a 256M-bit DRAM of the fourth generation is maximum in case of DRAMs, and is about 1.34 times more advantageous than that obtained by using a 6-inch square substrate. In case of LOGICs, throughputs are averagely improved by 1.25 times by using 9-inch square substrates than 6-inch square substrates, including a peak in which the throughput obtained by using a substrate of 9-inch square for the generation of 256M-bit is about 1.33 times more advantageous than that obtained by using a 6-inch square substrate.
In addition, supposing that a conventional mask of a 256M-bit DRAM of the first generation is $10,000 and that one mask is consumed per 25,000 wafers in case of DRAMs while one mask is consumed per 2,000 wafers in case of LOGICs, the cost performance of lithography is expressed as a (throughput).times.(chips per wafer)/((a cost for an exposure apparatus)+(a cost for a mask)+(a cost for processing)). Values thus obtained are respectively defined, depending on values for the 256M-bit type of the first generation, for each of cases of DRAMs and LOGICs, and are indicated for each of sizes of masks. The following tables 7 and 8 show the results.
TABLE 7 __________________________________________________________________________ Cost-performance of DRAMs __________________________________________________________________________ 256 M 1 G First Second Third Fourth First Second DRAM 64 M Generation Generation Generation Generation Generation Generation __________________________________________________________________________ REGION SIZE 7 .times. 13 13 .times. 25 11 .times. 22 10 .times. 19 8 .times. 17 15 .times. 31 14 .times. 25 (mm .times. mm) Exposure 25 mm .times. Scanning Length 30 mm .times. Scanning Length Region 6-inch 3.03 1 1.14 1.43 1.87 .64 0.76 Square 7-inch 3.33 1.08 1.21 1.50 1.70 0.61 0.72 Square 8-inch 3.13 1.01 1.22 1.40 1.81 0.57 0.73 Square 9-inch 2.92 0.95 1.14 1.39 2.05 0.65 0.79 Square __________________________________________________________________________ 1 G 4 G Fourth First Second Third Fourth DRAM Third Generation Generation Generation Generation Generation Generation __________________________________________________________________________ REGION SIZE 12 .times. 23 10 .times. 20 19 .times. 38 17 .times. 33 14 .times. 29 12 .times. 25 (mm .times. mm) Exposure 30 mm .times. Scanning 35 mm .times. Scanning Length Region Length 6-inch 0.82 Square 7-inch 0.89 1.16 0.20 0.36 0.42 0.49 Square 8-inch 0.93 1.41 0.31 0.34 0.46 0.60 Square 9-inch 0.87 1.33 0.29 0.35 0.44 0.70 Square __________________________________________________________________________
TABLE 8 ______________________________________ Cost performance of LOGICs ______________________________________ LOGIC 256 M 1 G 4 G Region Size 19 .times. 19 21 .times. 21 23 .times. 23 (mm .times. mm) Exposure 25 mm .times. Scanning 30 mm .times. 35 mm .times. Region Length Scanning Length Scanning Length 6-inch Square 1 0.72 -- 7-inch Square 0.85 0.64 0.41 8-inch Square 0.96 0.67 0.35 9-inch Square 0.81 0.57 0.35 ______________________________________
Here, from the cost-performance of DRAMs shown in the above Table 7, a large difference cannot be found between the case of a 9-inch square mask achieving a merit from the fourth generation of 256M-bit to the second generation of 1 G-bit and the case of a 8-inch square mask achieving a merit from the third generation of 1 G-bit to the first generation of 4 G-bit, since both cases are 1.07 times more advantageous, when thinking of averages of both cases. In addition, as shown in Table 8, in the case of LOGICs, it can be found that a 6-inch square mask attains the greatest merit for the generations equivalent to 256M-bit and 1 G-bit types, and a 7-inch square mask attains the greatest merit for the generations equivalent to the 4 G-bit type.
Therefore, from the aspects of costs and merits, it is considered that the most advantageous way is considered to use an exposure apparatus corresponding to a 8-inch square or 9-inch square substrate in case of manufacturing a DRAM and to use an exposure apparatus corresponding to a 6-inch square or 7-inch square substrate in case of manufacturing a LOGIC. However, since the cases where merits are obtained are different between the exposure apparatuses, it is not possible to consistently chose which mask or exposure apparatus should be used.
Since a drawing apparatus, a measurement apparatus, a defect inspection apparatus, or a repair apparatus, as a mask manufacture apparatus, is applicable to several sizes of substrates, it is possible to mix and use 6-inch square substrates, 7-inch square substrates, 8-inch square substrates, and 9-inch square substrate with each other. However, since a mask stage of an exposure apparatus requires an apparatus, such as a vacuum chuck or the like, for fixing a substrate immediately outside an exposure region, the mask stage is not designed so as to apply to a plurality of sizes of substrates. Therefore, discussions have been made as to whether all the production lines should be arranged so as to correspond to 9-inch square substrates with merits maintained for DRAM production and another exposure apparatus for manufacturing LOGICs of different models and of small production should be prepared, or all the exposure apparatus should be arranged so as to correspond to 6-inch square substrates at the sacrifice of merits of manufacturing DRAMs.
Further, based on the current situation, there is a remarkable difference in demands for DRAMs between when the market is active and when the market is inactive. Therefore, the market of the semiconductor industry changes up and down very harshly. In recent days, DRAMs are manufactured at full power when the market is active, and a part of the production system is switched to manufacture of LOGICs whose market is stable, when the market is inactive. In other words, since no factory can operate only for DRAMs, a factory capable of efficiently manufacturing DRAMs and LOGICs together is necessary.
Thus, as for transfer of circuit patterns of semiconductor devices, there are different optimal mask sizes which maximizes the cost-merit, respectively, for types of DRAM and LOGIC and for each of generations, while one pattern transfer apparatus permits its own mask size and therefore adopts only one mask size. In case where one kind of semiconductor devices is to be manufactured, a corresponding pattern transfer apparatus is used. However, in case of manufacturing several types of semiconductor devices, it is not possible to efficiently manufacture all the types of semiconductor devices even if a pattern apparatus of any pattern size is selected.